The present invention relates to a semiconductor integrated circuit, and more specifically to a microprocessor and its peripheral integrated circuits.
In an information processing device incorporating a microprocessor, normal and abnormal states of the device are monitored. This is accomplished by monitoring bits in a status register by executing a polling routine or an interrupt routine. One example of a normal state is a state in which a communication buffer is empty. An example of an abnormal state is a state in which there is CRC data or the like in received data. Software processing is performed accordingly based on this monitoring. In this way, debugging is necessary when developing a device, and a change in the status bit caused by an error that should not occur in a normal state must be checked. Therefore, an equivalent register space is prepared in the system memory, and this memory space is assumed to be a status register. The value of the status register is re-written to cause a change in status register in a falsified manner and perform debugging of the monitoring subject.
Japanese Laid-Open Patent Publication No. 2005-006394 describes a technique providing a memory chip for reducing the testing time and testing cost of memory cells. In this technique, a semiconductor memory chip includes a memory array of test memory devices, a pattern generator for providing reference data that is input and stored in the memory array, and a comparator formed on the memory chip to compare the stored data from the memory array with the reference data. The comparator includes a logic circuit for comparing the reference data and the stored data and generating a comparison result that indicates whether the data match, a plurality of latches shifted between first and second states and receiving comparison results from the logic circuit, and registers for storing and outputting the first and second states of the latches to generate test results.
A test circuit such as that shown in FIG. 4 is incorporated in part of a semiconductor integrated circuit to check the legitimacy of a detection function related to abnormal errors. Debugging is performed by partially changing a status bit with this function. The circuit includes a data error insertion unit 11, a data write processing unit 12, a receiving buffer 13, a CRC inspection unit 14, and a packet length inspection unit 15, a CRC test register 110, packet length test register 111, CRC error status register 120, and packet length error status register 121. In the data error insertion unit 11, the data stored in the CRC test register 110 is added to the received data. The data stored in the packet length test register 111 is added in the data write processing unit 12. When a CRC error is detected in the CRC inspection unit 14, the result is stored in the CRC error status register 120. When a packet length error is detected in the packet length inspection unit 15, the result is stored in the packet length error status register 121.
Japanese Laid-Open Patent Publication No. 2003-178596 describes a semiconductor integrated circuit capable of resolving a deficiency quickly and inexpensively even when a bug is found in a final manufacturing stage. The semiconductor integrated circuit includes a ROM for storing a program, a microprocessor for executing a program code read from the ROM, a substitution code register for storing a substitution code that is substituted for the program code, and a substitution address designation register for storing an address substituted for the program code. The comparator compares the read address output to an address bus with the address stored in the substitution address designation register. Based on the comparison result, a selector selects whether to provide the program code executed by the microprocessor from the ROM or from the substitution code register side.
As described above, in a method for temporarily allocating a status register in a memory, it is necessary to perform many program rewrites for software debugging.
Further, there is a possibility of contamination by new bugs when returning to the original state after debugging is completed.
Furthermore, since status changes occur in a system memory, there is a possibility of overlooking problems that occur between the microprocessor and the actual semiconductor integrated circuit. This affects the inspection quality of the hardware and software as a whole. Although test circuits may be prepared for the entire status register space in the semiconductor integrated circuit when a new semiconductor integrated circuit is designed, this would increase the test circuit scale. Further, in the limited register space, much space would be occupied for testing.